Jade Design Automation

Tools designed for engineers

The Register Management Expert

Jade Design Automation has a laser sharp focus on register management with a mission to address the register management challenges from system architecture to SW bring-up. Addressing the most difficult problems in this field like the configurability and customizability of processor registers including the RISC-V CSRs. Within the semiconductor industry we are working with blue-chip SoC companies covering the whole process from system architecture to board bring-up as well as design service companies offering system integration or full ASIC solutions and IP companies providing high quality IPs to SoCs.

Register Manager

Peripheral IP view of the Register Manager EDA tool

What does Register Manager do?

Register Manager, the flagship product of Jade Design Automation, efficiently manages all tasks around the HW/SW interface of an SoC. The users can capture register and bitfield information on the IP level as well as the memory maps on the IP, subsystem and SoC level. It generates RTL, Verification, SW, Documentation and Interoperability formats like IP-XACT 1685-2009 and 1685-2014 from these descriptions. On top of the IP-XACT and SystemRDL importers, legacy data in custom formats can be imported via the tool’s API.

Performance metrics of the Register Manager EDA tool


Register Manager has a rich and intuitive GUI to instantly visualize and edit the HW/SW interface. The tool also has a fully functional shell mode for power users as well as fully scriptable command files for automated flows. Register Manager is IoT ready with out-of-box support for Arm’s TrustZone® technology built on the v8-M architecture on AMBA® based systems. It is lightweight and performant and can capture, validate, generate Verilog, UVM, C-headers and documentation for a IoT SoC in a few seconds.

System view of the Register Manager EDA tool

Who is the tool for?

The tool addresses the requirements of System Architects who can capture the high level design in a top-down approach. It is also a great productivity booster for IP teams who can auto-generate production ready Verilog and UVM register descriptions throughout the development process. System Integrators can use the tool to pull together IPs from various sources to a single platform to increase the quality of the system.

Note: Several of the screenshots on this page the the Register Manager page refer to data and IP that belongs to Arm. In particular, Arm and AMBA and TrustZone are registered trademarks of Arm while CMSDK_TIMER, UART_PL011, SSE-200 and v8-M are Arm product names. Every description, name and data that belongs to Arm and that is visible on these screenshots come from the publicly available non-confidential documentation from infocenter.arm.com and their copyright belongs to Arm. All the above mentioned trademarks and product names are used in good faith and in accordance with policies published on Arm’s website. Showing these here are purely for illustrative purposes and they don’t mean endorsement from Arm in any way.